RTL Verification using System Verilog
Program Outcomes
At the completion of the program, learners will be able to:
Develop synthesizable RTL code using Verilog HDL, applying correct modelling styles, sensitivity handling, and timing constructs.
Apply System Verilog features such as arrays, queues, classes, and OOP concepts to construct scalable and reusable testbenches.
Use assertions, constraints, and randomization techniques to perform functional verification.
Simulate, debug, and verify digital designs using EDA tools and analyze behavior through waveform.
Indicative Content
Verilog HDL
- Verilog Module
- Data Types Operators
- Modelling Styles
- RTL Coding guidelines
- Continuous assignments
- Procedural blocks
- Sensitivity list
- Blocking and Non-Blocking Statements
- Inter and Intra delay statements
- Race conditions
- Compiler directives
- System tasks
- Arrays Tasks and Functions
- Introduction to EDA Tools
System Verilog & FPGA
- Introduction to System Verilog
- Data Types
- Arrays Queues
- Structures
- Unions
- Procedural Statements and Control flow
- Testbench Architecture
- Program Blocks, Interfaces, Classes, MailBoxes, Clocking block
- OOPS concepts – Polymorphism, Encapsulation, Inheritance, Abstraction Processes
- Assertions
- Constraints
- Randomization
- Interprocess Communication
- Verification Project using System Verilog