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ASIC Prototyping on FPGA

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ASIC Prototyping on FPGA

TBA 4 Months

At the completion of the program the learners will be able to:

Apply the ASIC design flow by prototyping RTL designs on FPGA using Verilog HDL. Demonstrate the ability to translate design specifications into synthesizable hardware, progressing through design entry, functional simulation, and hardware validation stages

Utilize EDA tools to perform synthesis, simulation, and static timing analysis. Analyze timing reports and simulation results to validate functionality and timing closure, while ensuring design quality through Lint, Clock Domain Crossing, and Reset Domain Crossing checks

Construct and integrate FSMs, subsystems, and IP blocks into larger digital systems. Interface and validate communication with peripherals using UART, SPI, I2C protocols, and analyze the integration of bus protocols like AXI, AHB, and APB for efficient data transfer

Implement basic RISC-V based designs on FPGA and analyze system behavior through testbenches and debugging techniques. Develop automation scripts using Linux shell and TCL, while enhancing employability through structured resume building and mock interview practice
Indicative Content

Foundation

  • Linux Essentials
  • TCL Scripting
  • Digital Design
  • Static Timing Analysis Verilog HDL Basics
  • Static Timing Analysis
  • Verilog HDL Basics

Core Modules

  • High Speed Digital Design
  • FSM Introduction to ASIC and FPGA
  • Introduction to Computer Architecture
  • Specification and Architectural Design
  • Introduction to EDA Tools RTL Design and Verification Lint, CDC & RDC Introduction to Synopsys Design Constraints Synthesis
  • Introduction to Memory Peripheral and Subsystem Integration

Advance Modules

  • Bus Interfaces and Interconnects Communication
  • Protocols (UART, SPI, I2C, USB)
  • Bus Protocols (APB, AXI4, AHB)
  • Advanced Topics in SoC
  • RISCV Architecture
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