Physical Design and Verification
At the completion of the program the learners will be able to:
Discuss the core concepts of physical design principles, device physics, CMOS and advanced CMOS technologies including FinFET, GAA, SOI and scripting languages like Python and TCL
Apply core concepts of digital logic, synthesis, timing and power analysis to design, implement, and validate full-custom and semi-custom digital ICs using industry-standard EDA tools
Implement Design for Test concepts, including scan chain insertion, ATPG , and BIST in scenarios mimicking realistic tapeout processes
Develop complete physical design flows, including floorplanning, Placement and Routing , Clock Tree Synthesis , power, Performance and area, Engineering Change Orders , and signoff methodologies
Implement the complete ASIC physical design flow from netlist to GDSII using industry tools e.g., Cadence Innovus, Synopsys , including physical verification steps like DRC, LVS, ERC, and Antenna Checks, and resolving associated violations
Perform Static Timing Analysis and power-aware validation while addressing critical design metrics such as IR drop, crosstalk, routing congestion, signal integrity, and parasitics
Analyze post-layout simulation results under PVT variations, iterate to meet performance targets, and apply mitigation techniques for challenges in advanced technology nodes
Indicative Content
Foundation
- Linux Essentials
- Python Scripting
- TCL Scripting
- Digital Electronics
- High Speed Digital Design
- Logic Design
- Circuit Theory
- Network Theory
- Verilog for Synthesis
Advanced Microelectronics
- Introduction to Microelectronics
- MOSFET
- MOSFET as Switch, Capacitor, Amplifier
- Long Channel & Short Channel Effects
- Small Signal Analysis
- Emerging MOS Devices – CFET, GAA, FinFET
- SOI (Silicon-on-Insulator) Technology
- FD-SOI vs Bulk CMOS
- Advanced CMOS Nodes (5nm, 3nm, 2nm)
- Process Variations & Reliability Analysis
- Layout Dependent Effects - WPE, PPE, LOD
- Noise Mitigation Techniques
- 3D IC, Chiplet & Heterogeneous Integration
Synthesis & DFT
- Introduction to Synthesis
- Flow Introduction to EDA Tools
- Timing Libraries
- Constraint Setup & Optimization Techniques
- Lint & Clock Domain Crossing
- Generating Netlist & Reports
- Static Timing Analysis
- Low Power Analysis
- UPF
- Introduction to DFT
- Scan Chain Insertion, Scan Compression
- Fault Models, ATPG
- BIST Architecture
Physical Design & Verification
- Physical Design Process
- Initial Design
- Floorplan
- Powerplan
- Placement Routing
- Synthesis
- Engineering Change Order (ECO)
- Physical Verification – DRC, LVS, Antenna Check, ERC, LEC
- Parasitic Extraction
- Back Annotation
- Power, Timing, Signal Integrity (SI), EM/IR Analysis
- Signoff
- Project