The objectives of the programs under this domain are to equip students with the knowledge and skills to critically evaluate and design advanced semiconductor systems across three key domains:Analog Layout, RTL Design & Verification, and Physical Design.The Programs will focus on emerging CMOS technologies such as FinFET, GAA, SOI, and CFET, providing students with a comprehensive understanding of these cutting-edge advancements.
In the Analog Layout domain, students will synthesize complex analog circuits, including Op-amps, LDOs, LNAs, PLLs, and data converters, thereby gaining hands-on experience in the design and optimization of these critical building blocks for semiconductor systems.
In the RTL Design & Verification domain, they will acquire proficiency in digital design and verification using Verilog, SystemVerilog, and UVM , applying appropriate industry-standard techniques.
The Physical Design domain will cover principles such as Floor Planning, Place and Route, Power Planning, and Timing analysis, utilizing state-of-the-art EDA tools. Validation of designs through DRC, LVS, LEC, PEX and DFM will be emphasized to ensure manufacturability and robustness.
The Programs will also enhance students' scripting skills in Python, TCL, and Linux, providing career development support like Resume Preparation, Mock Interviews and Soft Skills training to prepare them for industry roles. By the end of the Programs, students will be proficient in designing optimized IPs, validating complex systems, and contributing to the advancement of semiconductor technologies, positioning them to be highly competitive in the industry.
| Program Name | Commencement | Duration | Enroll |
|---|---|---|---|
| Advanced Analog Layout Design | TBA | 6 Months | Enroll Now |
| ASIC RTL Design and Verification | Nov 2025 | 6 Months | Enroll Now |
| Physical Design and Verification | TBA | 6 Months | Enroll Now |
| ASIC Prototyping on FPGA | TBA | 4 Months | Enroll Now |
| FPGA Implementation with Verilog HDL | 4th Aug 2025 | 1 Month | Enroll Now |
| RTL Verification using System Verilog | TBA | 1 Month | Enroll Now |
* The duration of our outcome-based Program may vary depending on the learner’s pace and progress.