ASIC RTL Design and Verification
Program Outcomes
At the completion of the program the learners will be able to:
At the completion of the program the learners will be able to:
Discuss the foundational concepts in digital design and scripting languages like TCL, Python, Linux, Verilog, SystemVerilog, UVM constrained randomization, functional coverage, assertions, DPI, and formal verification
Develop synthesizable RTL designs and construct reusable and scalable UVM-based testbenches to verify design correctness and corner cases
Apply verification methodologies including constrained random testing, coverage analysis, and assertion-based verification
Identify and resolve functional issues using simulation and debugging tools
Analyze formal verification methods to ensure implementation readiness
Apply synthesis-driven design principles, verification of IPs and SoC-level components using AMBA protocols, and coverage analysis to ensure functional correctness
Indicative Content
Foundation
- Linux Essentials
- TCL & Python Scripting
- Digital Design
- High Speed Digital Design
- Static Timing Analysis
- Verilog HDL Basics
- Introduction to EDA tools
Verilog & SystemVerilog
- Verilog for Synthesis
- Verilog based Design & Verification
- SystemVerilog Basics
- Introduction
- Testbench
- Architecture
- Interfaces & Classes
- OOP Concepts
- Assertions Arrays
- Advanced SystemVerilog
- Procedural Statements & Routines
- Threads and IPC
- Direct Programming Interface (DPI)
- Randomization & Constraints
- Code & Functional Coverage
- Formal Verification
- Assertion Based Verification
- Coverage Driven Verification
- AMBA Protocols
UVM
- Introduction to UVM
- UVM Testbench Architecture
- UVM Base Classes
- UVM Phases & Reporting Mechanisms
- Transaction Level Modelling
- Factory Registration & Methods
- Virtual Sequence & Sequencer
- Register Abstraction Layer
- Config DB
- Project